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RF1450
SP4T SWITCH
RoHS Compliant & Pb-Free Product Package Style: QFN, 16-pin, 3mmx3mm
VBAT
GND 14
pHEMT Switch
RF2
Features
Low Insertion Loss 0.4dB @ 1GHz High Isolation 29dB @ 1GHz VDD =2.5V to 2.85V, Down to 1.8V with Reduced Specifications High Linearity IMD <-110dBm Harmonics: -75dBc@1GHz GaAs pHEMT Process
GND 1 VDD 2 CTRL2 3 CTRL1 4
16
15
13 12 GND 11 ANT 10 GND
CMOS Decoder
RF1 9 GND 8 RF3
5 GND
6 RF4
7 GND
Applications
Cellular Handset Applications Multi-Mode GSM, W-CDMA Applications GSM/GPRS/EDGE Switch Applications Cellular Infrastructure Applications
Functional Block Diagram
Product Description
The RF1450 is a single-pole four-throw (SP4T) high power switch specially designed to handle GSM power applications. Excellent linearity performance achieved by the RF1450 makes it ideal for multimode GSM/EDGE/W-CDMA applications. Additionally, RF1450 includes integrated decoding logic, allowing just two control lines needed for switch control. The RF1450 is packaged in a very compact 3mmx3mmx0.9mm, 16-pin, leadless QFN package.
Ordering Information
RF1450SP4T Switch
RF1450 RF1450PCBA-410
SP4T Switch Fully Assembled Evaluation Board
Optimum Technology Matching(R) Applied
GaAs HBT GaAs MESFET InGaP HBT SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT
RF MICRO DEVICES(R), RFMD(R), Optimum Technology Matching(R), Enabling Wireless ConnectivityTM, PowerStar(R), POLARISTM TOTAL RADIOTM and UltimateBlueTM are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. (c)2006, RF Micro Devices, Inc.
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Absolute Maximum Ratings Parameter
VBATT VDD Maximum Input Power (0GHz to 2GHz, 2.5V Control) Operating Temperature Storage Temperature
Rating
6.0 3.0 +36 -20 to +85 -35 to +100
Unit
V V dBm C C
Caution! ESD sensitive device.
The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice. RoHS status based on EUDirective2002/95/EC (at time of this document revision).
Parameter
Min.
Specification Typ.
Max.
Unit
Condition
Active Mode: VHIGH >1.3V, VLOW <0.05V; Temp=25C; VDD =2.5V to 2.85V PIN =34.5dBm@0.9GHz or 31dBm@1.8GHz; All RF ports terminated to ZO =50.
Electrical Characteristics
Insertion Loss 0.5GHz to 1.0GHz 1.0GHz to 2.0GHz 2.1GHz 2.5GHz Isolation 0.5GHz to 1.0GHz 1.0GHz to 2.0GHz 2.1GHz 2.5GHz RF Port Return Loss 0.5GHz to 2.2GHz 15 37 34 -80 -85 Third Harmonic (3f0) IMD -80 -80 -110 dB dBm dBm dBc dBc dBc dBc dBm 27 22 21 19 29 24 23 21 dB dB dB dB 0.40 0.45 0.50 0.60 0.55 0.60 0.65 0.90 dB dB dB dB
All RF ports in Insertion Loss state. f=0.9GHz f=1.8GHz f=0.9GHz, PIN =34.5dBm f=1.8GHz, PIN =31.5dBm f=0.9GHz, PIN =34.5dBm f=1.8GHz, PIN =31.5dBm Fundamental Frequency Power Level=+20dBm @ 1950MHz Blocker Power Level=-15dBm @ 1760MHz VSWR>20; f=0.9GHz VSWR>20; f=1.8GHz Maximum set up time for the switch to reach fully compliant operation
Operating Characteristics
Input Power at 0.1dB Compression Point Second Harmonic (2f0)
Power Handling in Mismatched Condition Switching Speed Start-up Time
34.5 31.0 5 25
dBm dBm s s
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Parameter
VDD=1.8V<2.5V, Temp=25C
Second Harmonic 2f0 Third Harmonic 3f0 IMD -80 -80 -75 -75 -105 dBc dBc dBc dBc dBm f=0.9GHz, PIN =34.5dBm f=1.8GHz, PIN =31.5dBm f=0.9GHz, PIN =34.5dBm f=1.8GHz, PIN =31.5dBm Fundamental Frequency Power Level=+20dBm @ 1950MHz Blocker Power Level=-15dBm @ 1760MHz
Min.
Specification Typ.
Max.
Unit
Condition
Supply and Control Signal Characteristics
Supply Voltage (VBAT) Supply Current (VBAT) Standby Mode Active Mode Switched Supply Voltage (VDD) VHIGH VLOW Switched Supply Current (VDD) IHIGH ILOW Control Voltage (CTRL1, CTRL2) VHIGH VLOW Control Current (CTRL1, CTRL2) IHIGH ILOW 0.5 0.5 A A 1.3 0 2.7 0.05 V V 160 0 250 A mA 1.80 2.50 0 2.85 0.05 V V With reduced specifications below 2.5V VDD, see electrical parameters table. 0.55 0.1 1.50 A A 2.9 4.4 V
*Through phase is defined as measured normalized using a reference calibration PWB.
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Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pkg Base Function GND VDD CTRL2 CTRL1 GND RF4 GND RF3 GND GND ANT GND RF1 GND RF2 VBAT GND Description
Ground. Supply. The voltage at this node will be switched and it is important that the switch is operating within the specified start up time. This signal might be used as a mode control. Control signal 2. Control signal 1. Ground. RF output 4. Ground. RF output 3. Ground. Ground. RF input (connected to antenna). Ground. RF output 1. Ground. RF output 2. Constant supply. Ground.
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RF1450
Pin Out
VBAT GND 14 RF2 RF1 13 12 GND 11 ANT 10 GND 9 GND 5 GND 6 RF4 7 GND 8 RF3
16 GND 1 VDD 2 CTRL2 3 CTRL1 4
15
Package Drawing
Pin 1
3.000 0.050
0.203 0.013 TYP.
3.000 0.050
Dimensions in mm.
0.850 0.050
Shaded lead is pin 1.
0.230 0.050 TYP
0.375 0.050 TYP
0.500 TYP 1.700 0.150 2 PL
1.500 REF
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General Information
Control Logic The switch is operable in four states (see Truth table, below). The switch is designed for two modes: Active and Stand-by. These modes are controlled by the VDD signal. When VDD is high, the switch is active. The start-up time is defined as the switch activated is critical. Truth Table for Switch States
State 1 2 3 4 CTRL1 VLOW VLOW VHIGH VHIGH CTRL2 VLOW VHIGH VLOW VHIGH RF Path ANT-RF1 ANT-RF2 ANT-RF3 ANT-RF4
Turn On Sequence
VBATT 1 2 3 4 ON X X X VDD OFF ON X X CTRL1 OFF OFF ON X CTRL2 OFF OFF ON X RF Power OFF OFF OFF ON
Turn Off Sequence
VBATT 1 2 3 4 ON ON ON OFF VDD ON ON OFF X CTRL1 ON OFF X X CTRL2 ON OFF X X RF Power OFF X X X
Note: VBATT must be applied before applying VDD when turning on the part. The part must be turned off in reverse order, VDD first then VBATT. Electrical Test Methods The electrical parameters for the switch were measured on test PWB provided by the switch supplier. The test PWB includes means for decoupling RF signals from control signal port (shunt capacitor at control signal ports). All measurements are done with calibration plane at switch pins. The effect of test board losses and phase delay has been removed from the results. Reflected Harmonics Measurement The reflected harmonics should be measured with the output ports connected to open-circuit or short-circuit impedances. An outline of the measurement set-up is shown in Figure 1. The power in and reflected signal levels are calibrated to the DUT input (reference plane). Note that the power is calibrated in a 50 system. The assumption is made that the measurement system is designed so that the harmonic levels of external PA, etc., are far below the signals produced by the DUT.
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The phase delay for RFOUT1 is altered between 0 and 360, so that all possible load phases are scanned. The VSWR at the connection shall be 20:1@0.9GHz, 15:1@1.8GHz. The other outputs, shall be connected to open-circuit (PIN left open) or signal ground; both options should be tested. After testing RFOUT1, the same test should be done for the other outputs.
Measure Harmonic Signal
Reflected Signal
RF1 RF2 RF3 RF4 Delay Line
Open-circuit or Short-circuit
Attenuator
Directional Coupler Reference Plane
DUT
Figure 1. Reflected Harmonics Measurement Set-up
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Application Schematic
RF2 100 pF VBAT 100 pF 1 10 KpF VDD CTRL2 100 pF 3 4 5 CTRL1 100 pF 100 pF 100 pF 6 7 8 10 9 2 16 15 14 13 12 100 pF 11 CESD= 0.75 pF LESD= 12 uH ANT 100 pF RF1
RF4
RF3
Application Diagram and Guidelines The decoupling capacitors are optional and, if necessary, may be used for noise reduction. Decoupling capacitors on the control pins protect the control circuitry from possible RF leakage. An ESD filter is needed to protect the switch from antenna ESD events. The filter is formed by LESD inductor and CESD capacitor. The switch has a supply input to feed the built-in logic decoding.
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Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.0658", Board Material FR-4
Component Layer Topside RF Layer
Ground Plane Layer
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Typical Performance
Return Loss
0.0 0.0
Insertion Loss
-5.0
-10.0
dB
dB
-15.0 -20.0 -25.0 400.0 900.0 1400.0 1900.0 2400.0 2900.0
-1.0
-2.0 400.0 900.0 1400.0 1900.0 2400.0 2900.0
MHz
MHz
Isolation
0.0 -5.0 -10.0 -15.0 -20.0
dB
-25.0 -30.0 -35.0 -40.0 -45.0 -50.0 400.0 900.0 1400.0 1900.0 2400.0 2900.0
MHz
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RF1450
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns for RFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. PCB Metal Land Pattern
A = 0.64 x 0.28 Typ. B = 0.28 x 0.64 Typ. C = 1.70 Sq.
Dimensions in mm.
0.50 Typ.
Pin 16
B
Pin 1
B
B
B
Pin 12
A 0.50 Typ. A C A A 0.55 Typ. B B B B
Pin 8
A A A A
0.75 1.50 Typ.
0.55 Typ. 0.75 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
Rev A0 DS070531
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PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.74 x 0.38 Typ. B = 0.38 x 0.74 Typ. C = 1.70 Sq.
Dimensions in mm.
1.50 Typ. 0.50 Typ.
Pin 16 Pin 1
BBBB A A A A C BBBB
Pin 12
0.50 Typ.
0.55 Typ.
A A 0.75 Typ. 1.50 Typ. A A
Pin 8
0.75 Typ. 0.55 Typ.
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
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